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slus507d ? january 2002 ? revised november 2005 1 www.ti.com features operating input voltage 2.25 v to 5.5 v output voltage as low as 0.7 v 1% internal 0.7 v reference predictive gate drive n-channel mosfet drivers for higher efficiency externally adjustable soft-start and overcurrent limit source-only current or source/sink current versions for starting into v out pre-bias 10-lead msop powerpad package for higher performance thermal shutdown internal boostrap diode fixed-frequency, voltage-mode control ? TPS40000/1/4 300-khz ? tps40002/3/5 600-khz simplified application diagram applications networking equipment telecom equipment base stations servers dsp power power modules description the tps4000x are controllers for low-voltage, non-isolated synchronous buck regulators. these controllers drive an n-channel mosfet for the primary buck switch, and an n-channel mosfet for the synchronous rectifier switch, thereby achieving very high-efficiency power conversion. in addition, the device controls the delays from main switch off to rectifier turn-on and from rectifier turn-off to main switch turn-on in such a way as to minimize diode losses (both conduction and recovery) in the synchronous rectifier with ti?s proprietary predictive gate drive technology. the reduction in these losses is significant and increases efficiency. for a given converter power level, smaller fets can be used, or heat sinking can be reduced or even eliminated. udg?01141 v in v out 1 ilim 10 boot 2fb 9 hdrv 3 comp 8 sw 4 ss/sd 7 vdd 5 gnd 6 ldrv TPS40000 copyright ? 2005, texas instruments incorporated powerpad and predictive gate drive are trademarks of texas instruments incorporated.
slus507d ? january 2002 ? revised november 2005 2 www.ti.com description (continued) the current-limit threshold is adjustable with a single resistor connected to the device. the tps4000x controllers implement a closed-loop soft start function. startup ramp time is set by a single external capacitor connected to the ss/sd pin. the ss/sd pin is also used for shutdown. ordering information packaged devices msop (2) (dgq) application t a frequency source only source/sink with prebias (3) source/sink (3) ?40 c to 85 c 300 khz TPS40000dgq tps40001dgq tps40004dgq ?40 c to 85 c 600 khz tps40002dgq tps40003dgq tps40005dgq (2) the dgq package is available taped and reeled. add r suffix to device type (e.g. TPS40000dgqr) to order quantities of 2,500 devices per reel and 80 units per tube. (3) see application information section, p. 8. absolute maximum ratings over operating free-air temperature range unless otherwise noted (1) tps4000x unit boot v sw + 6.5 comp, fb, ilim, ss/sd ?0.3 to 6 input voltage range, v in sw ?0.7 to 10.5 v input voltage range, v in sw t (sw transient < 50 ns) ?2.5 v vdd 6 operating junction temperature range, t j ?40 to 150 storage temperature, t stg ?55 to 150 c lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 c (1) stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating con ditions? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. actual size 3,05mm x 4,98mm 1 2 3 4 5 10 9 8 7 6 ilim fb comp ss/sd gnd boot hdrv sw vdd ldrv dgq package (4).(5 ) (top view) (4) see technical brief slma002 for pcb guidelines for powerpad packages. (5) powerpad heat slug can be connected to gnd (pin 5).
slus507d ? january 2002 ? revised november 2005 3 www.ti.com electrical characteristics over recommended operating temperature range, t a = ?40 c to 85 c, v dd = 5.0 v, all parameters measured at zero power dissipation (unless otherwise noted) input supply parameter test conditions min typ max unit v dd input voltage range 2.25 5.5 v v hgate high-side gate voltage v boot ? v sw 5.5 v shutdown current ss/sd = 0 v, outputs off 0.25 0.45 i dd quiescent current fb = 0.8 v 1.4 2.0 ma i dd switching current no load at hdrv/ldrv 1.5 4.0 ma uvlo minimum on-voltage 1.95 2.05 2.15 v hysteresis 80 140 200 mv oscillator parameter test conditions min typ max unit f osc oscillator frequency TPS40000 tps40001 tps40004 2.25 v v dd 5.00 v 250 300 350 khz f osc oscillator frequency tps40002 tps40003 tps40005 2.25 v v dd 5.00 v 500 600 700 khz v ramp ramp voltage v peak ? v valley 0.80 0.93 1.07 v ramp valley voltage 0.24 0.31 0.41 v pwm parameter test conditions min typ max unit maximum duty cycle (2) TPS40000 tps40001 tps40004 fb = 0 v, v dd = 3.3 v 87% 94% 97% maximum duty cycle (2) tps40002 tps40003 tps40005 fb = 0 v, v dd = 3.3 v 83% 93% 97% minimum duty cycle 0% error amplifier parameter test conditions min typ max unit v fb fb input voltage line, temperature 0.689 0.700 0.711 v v fb fb input voltage t a = 25 c 0.693 0.700 0.707 v fb input bias current 30 130 na v oh high-level output voltage fb = 0 v, i oh = 0.5 ma 2.0 2.5 v v ol low-level output voltage fb =v dd , i ol = 0.5 ma 0.08 0.15 v i oh output source current comp = 0.7 v, fb = gnd 2 6 ma i ol output sink current comp = 0.7 v, fb = v dd 3 8 ma g bw gain bandwidth (1) 5 10 mhz a ol open loop gain 55 85 db (1) ensured by design. not production tested. (2) at v dd input voltage of 2.25 v, derate the maximum duty cycle by 3%.
slus507d ? january 2002 ? revised november 2005 4 www.ti.com electrical characteristics over recommended operating temperature range, t a = ?40 c to 85 c, v dd = 5.0 v, all parameters measured at zero power dissipation (unless otherwise noted) current limit parameter test conditions min typ max unit i sink ilim sink current v dd = 5 v 11 15 19 a i sink ilim sink current v dd = 2.25 v 9.5 13.0 16.5 a v os offset voltage sw vs ilim (1) 2.25 v v dd 5.00 ?20 0 20 mv v ilim input voltage range 2 vdd v t on minimum hdrv pulse time in overcurrent v dd = 3.3 v 200 300 ns sw leading edge blanking pulse in over- current detection 100 ns t ss soft-start capacitor cycles as fault timer (1) 6 rectifier zero current comparator parameter test conditions min typ max unit v sw sense voltage to turn off rectifier TPS40000 tps40002 ldrv output off ?15 ?7 ?2 mv sw leading edge blanking pulse in zero current detection 75 ns predictive delay parameter test conditions min typ max unit v swp sense threshold to modulate delay time ?350 mv t ldhd maximum delay modulation range time ldrv off ? to ? hdrv on 50 75 100 ns predictive counter delay time per bit ldrv off ? to ? hdrv on 3.0 4.5 6.2 ns t hdld maximum delay modulation range hdrv off ? to ? ldrv on 40 65 90 ns predictive counter delay time per bit hdrv off ? to ? ldrv on 2.4 4.0 5.6 ns shutdown parameter test conditions min typ max unit v sd shutdown threshold voltage outputs off 0.09 0.13 0.205 v v en device active threshold voltage 0.14 0.17 0.235 v soft start parameter test conditions min typ max unit i ss soft-start source current outputs off 2.0 3.7 5.4 a v ss soft-start clamp voltage 1.1 1.5 1.9 v bootstrap parameter test conditions min typ max unit r boot bootstrap switch resistance v dd = 3.3 v 50 100 ? ? (1) ensured by design. not production tested. (2) at v dd input voltage of 2.25 v, derate the maximum duty cycle by 3%.
slus507d ? january 2002 ? revised november 2005 5 www.ti.com electrical characteristics over recommended operating temperature range, t a = ?40 c to 85 c, v dd = 5.0 v, all parameters measured at zero power dissipation (unless otherwise noted) output driver parameter test conditions min typ max unit r hdhi hdrv pull-up resistance v boot ?v sw = 3.3 v , i source = ?100 ma 3 5.5 r hdlo hdrv pull-down resistance v boot ? v sw = 3.3 v , i sink = 100 ma 1.5 3 ? r ldhi ldrv pull-up resistance v dd = 3.3 v, i source = ?100 ma 3 5.5 r ldlo ldrv pull-down resistance v dd = 3.3 v, i sink = 100 ma 1.0 2.0 t rise ldrv rise time 15 35 t fall ldrv fall time c load = 1 nf 10 25 ns hdrv rise time c load = 1 nf 15 35 ns hdrv fall time 10 25 thermal shutdown parameter test conditions min typ max unit t sd shutdown temperature (1) 165 c hysteresiss (1) 15 c sw node parameter test conditions min typ max unit i sw leakage current in shutdown (1) 15 a (1) ensured by design. not production tested. (2) at v dd input voltage of 2.25 v, derate the maximum duty cycle by 3%.
slus507d ? january 2002 ? revised november 2005 6 www.ti.com terminal functions terminal i/o description name no . i/o description boot 10 o provides a bootstrapped supply for the topside mosfet driver, enabling the gate of the topside mosfet to be driven above the input supply rail comp 3 o output of the error amplifier fb 2 i inverting input of the error amplifier. in normal operation the voltage at this pin is the internal reference level of 700 mv. gnd 5 ? power supply return for the device. the power stage ground return on the board requires a separate path from other sensitive signal ground returns. hdrv 9 o this is the gate drive output for the topside n-channel mosfet. hdrv is bootstrapped to near 2 v dd for good en- hancement of the topside mosfet. ilim 1 i a resistor is connected between this pin and vdd to set up the over current threshold voltage. a 15- a current sink at the pin establishes a voltage drop across the external resistor that represents the drain-to-source voltage across the top side n-channel mosfet during an over current condition. the ilim over current comparator is blanked for the first 100 ns to allow full enhancement of the top mosfet. set the ilim voltage level such that it is within 800 mv of v dd ; that is, (v dd ? 0.8) i ilim v dd . ldrv 6 o gate drive output for the low-side synchronous rectifier n-channel mosfet ss/sd 4 i soft-start and overcurrent fault shutdown times are set by charging and discharging a capacitor connected to this pin. a closed loop soft-start occurs when the internal 3- a current source charges the external capacitor from 0.17 v to 0.70 v. during the soft-start period, the current sink capability of the tps40001 and tps40003 is disabled. when the ss/sd voltage is less than 0.12 v, the device is shutdown and the hdrv and ldrv are driven low. in normal opera- tion, the capacitor is charged to 1.5 v. when a fault condition is asserted, the hdrv is driven low, and the ldrv is driven high. the soft-start capacitor goes through six charge/discharge cycles, restarting the converter on the seventh cycle. sw 8 o connect to the switched node on the converter. this pin is used for overcurrent sensing in the topside n-channel mosfet, zero current sensing in synchronous rectifier n-channel mosfet, and level sensing for predictive delay circuit. overcurrent is determined, when the topside n-channel mosfet is on, by comparing the voltage on sw with respect to vdd and the voltage on the ilim with respect to vdd. zero current is sensed, when the rectifier n-channel mosfet is on, by measuring the voltage on sw with respect to ground. zero current sensing applies to the TPS40000/2 devices only. vdd 7 i power input for the chip, 5.5-v maximum. decouple close to the pin with a low-esr capacitor, 1- f or larger.
slus507d ? january 2002 ? revised november 2005 7 www.ti.com functional block diagram udg?01142 15 a 3 a 7 boot 10 vdd ilim 1 3 sw 8 comp 4 hdrv 9 ss/sd 5 ldrv 6 gnd uvlo vdd 2 v soft start 0.12 v shut down osc uvlo discharge ss active fault counter pwm comp pwm logic oc thermal shutdown clk uvlo predictive gate drive (vdd?1.2 v) current limit comp ldrv rectifier zero?current comparator vdd pwm lo vdd hi fault ldrv 100 ns delay en en 75 ns delay 2 fb + ref error amplifier 0.7 v +
slus507d ? january 2002 ? revised november 2005 8 www.ti.com application information the tps4000x series of synchronous buck controller devices is optimized for high-efficiency dc-to-dc conversion in non-isolated distributed power systems. a typical application circuit is shown in figure 1. the tps40004 and tps40005 are the controllers of choice for most general purpose synchronous buck designs. each operates in two quadrant mode (i.e. source or sink current) full time. this choice provides the best performance for output voltage load transient response over the widest load current range. the tps40001 and tps40003 add an additional feature: they operate in single quadrant mode (i.e. source current only) during converter startup, and then when the converter has reached the regulation point, the controllers change to operate in two quadrant mode. this is useful for applications that have outputs pre-biased at some voltage before the controller is enabled. when the tps40001 or tps40003 is enabled, it does not sink current during startup and therefore does not pull current from the pre-biased voltage supply. the TPS40000 and tps40002 operate in single quadrant mode (source current only) full time, allowing the paralleling of converters. single quadrant operation ensures one converter does pull current from a paralleled converter. a converter using one of these controllers emulates a non-synchronous buck converter at light loads. when current in the output inductor attempts to reverse, an internal zero-current detection circuit turns off the synchronous rectifier and causes the current flow in the inductor to become discontinuous. at average load currents greater than the peak amplitude of the inductor ripple current, the converter returns to operation as a synchronous buck converter to maximize efficiency. udg?02013 10 f 20 k 100 f 7.68 k ? 470 f 10 f 15.7 k ? 243 ? 10 k ? v out 1.8 v 10 a 1.0 h si4836dy ihlp5050ce?01 si4836dy 5 8 7 10 9 1 2 3 ilim fb comp gnd hdrv sw vdd ldrv 3.6 nf 4 4.7 nf ss/sd 6 boot 100 pf tps40001 100 nf 3.3 nf 3.3 ? v dd 3.0 v to 5.5 v figure 1. typical application circuit
slus507d ? january 2002 ? revised november 2005 9 www.ti.com application information error amplifier the error amplifier has a bandwidth of greater than 5 mhz, with open loop gain of at least 55 db. the comp output voltage is clamped to a level above the oscillator ramp in order to improve large-scale transient response. oscillator the oscillator uses an internal resistor and capacitor to set the oscillation frequency. the ramp waveform is a triangle at the pwm frequency with a peak voltage of 1.25 v, and a valley of 0.25 v. the pwm duty cycle is limited to a maximum of 95%, allowing the bootstrap capacitor to charge during every cycle. bootstrap/charge pump there is an internal switch between vdd and boot. this switch charges the external bootstrap capacitor for the floating supply. if the resistance of this switch is too high for the application, an external schottky diode between vdd and boot can be used. the peak voltage on the bootstrap capacitor is approximately equal to vdd. driver the hdrv and ldrv mosfet drivers are capable of driving gate-to-source voltages up to 5.5 v. at v in , = 5 v and using appropriate mosfets, a 20-a converter can be achieved. the ldrv driver switches between vdd and ground, while the hdrv driver is referenced to sw and switches between boot and sw. the maximum voltage between boot and sw is 5.5 v. synchronous rectification and predictive delay in a normal buck converter, when the main switch turns off, current is flowing to the load in the inductor. this current cannot be stopped immediately without using infinite voltage. for the current path to flow and maintain voltage levels at a safe level, a rectifier or catch device is used. this device can be either a conventional diode, or it can be a controlled active device if a control signal is available to drive it. the tps4000x provides a signal to drive an n-channel mosfet as a rectifier. this control signal is carefully coordinated with the drive signal for the main switch so that there is minimum delay from the time that the rectifier mosfet turns off and the main switch turns on, and minimum delay from when the main switch turns off and the rectifier mosfet turns on. this scheme, predictive gate drive delay, uses information from the current switching cycle to adjust the delays that are to be used in the next cycle. figure 2 shows the switch-node voltage waveform for a synchronously rectified buck converter. illustrated are the relative effects of a fixed-delay drive scheme (constant, pre-set delays for the turn-off to turn-on intervals), an adaptive delay drive scheme (variable delays based upon voltages sensed on the current switching cycle) and the predictive delay drive scheme. note that the longer the time spent in diode conduction during the rectifier conduction period, the lower the efficiency. also, not described in figure 2 is the fact that the predictive delay circuit can prevent the body diode from becoming forward biased at all while at the same time avoiding cross conduction or shoot through. this results in a significant power savings when the main mosfet turns on, and minimizes reverse recovery loss in the body diode of the rectifier mosfet.
slus507d ? january 2002 ? revised november 2005 10 www.ti.com application information udg?01144 gnd fixed delay adaptive delay predictive delay channel conduction body diode conduction figure 2. switch node waveforms for synchronous buck converter overcurrent overcurrent conditions in the tps4000x are sensed by detecting the voltage across the main mosfet while it is on. basic description if the voltage exceeds a pre-set threshold, the current pulse is terminated, and a counter inside the device is incremented. if this counter fills up, a fault condition is declared and the device disables switching for a period of time and then attempts to restart the converter with a full soft-start cycle.
slus507d ? january 2002 ? revised november 2005 11 www.ti.com application information detailed description during each switching cycle, a comparator looks at the voltage across the top side mosfet while it is on. this comparator is enabled after the sw node reaches a voltage greater than (v dd ?1.2 v) followed by a 100-ns blanking time. if the voltage across that mosfet exceeds a programmable threshold voltage, the current-switching pulse is terminated and a 3-bit counter is incremented by one count. if, during the switching cycle, the topside mosfet voltage does not exceed a preset threshold, then this counter is decremented by one count. (the counter does not wrap around from 7 to 0 or from 0 to 7). if the counter reaches a full count of 7, the device declares that a fault condition exists at the output of the converter. in this fault state, hdrv is turned off and ldrv is turned on and the soft-start capacitor is discharged. the counter is decremented by one by the soft start capacitor (c ss ) discharge. when the soft-start capacitor is fully discharged, the discharging circuit is turned off and the capacitor is allowed to charge up at the nominal charging rate. when the soft-start capacitor reaches about 700 mv, it is discharged again and the overcurrent counter is decremented by one count. the capacitor is charged and discharged, and the counter decremented until the count reaches zero (a total of six times). when this happens, the outputs are again enabled as the soft-start capacitor generates a reference ramp for the converter to follow while attempting to restart. during this soft-start interval (whether or not the controller is attempting to do a fault recovery or starting for the first time), pulse-by-pulse current limiting is in effect, but overcurrent pulses are not counted to declare a fault until the soft-start cycle has been completed. it is possible to have a supply attempt to bring up a short circuit for the duration of the soft start period plus seven switching cycles. power stage designs should take this into account if it makes a difference thermally. figure 3 shows the details of the overcurrent operation. udg?01145 0v v ts overcurrent cycle normal cycle internal pwm external main drive overcurrent threshold voltage (+) v ts (?) figure 3. switch node waveforms for synchronous buck converter
slus507d ? january 2002 ? revised november 2005 12 www.ti.com application information figure 4 shows the behavior of key signals during initial startup, during a fault and a successfully fault recovery. at time t0, power is applied to the converter. the voltage on the soft-start capacitor (v css ) begins to ramp up and acts as the reference until it passes the internal reference voltage at t1. at this point the soft-start period is over and the converter is regulating its output at the desired voltage level. from t0 to t1, pulse-by-pulse current limiting is in ef fect, and from t1 onward, overcurrent pulses are counted for purposes of determining a possible fault condition. at t2, a heavy overload is applied to the converter. this overload is in excess of the overcurrent threshold. the converter starts limiting current and the output voltage falls to some level depending on the overload applied. during the period from t2 to t3, the counter is counting overcurrent pulses, and at time t3 reaches a full count of 7. the soft-start capacitor is then discharged, the counter is decremented, and a fault condition is declared. v css v out i load udg?01144 t t0 t1 t2 t3 t10 0 6 5 4 3 2 1 0 t4 t5 t6 t7 t8 t9 1 2 3 4 5 6 7 0.7 v fault figure 4. switch node waveforms for synchronous buck converter when the soft start capacitor is fully discharged, it begins charging again at the same rate that it does on startup, with a nominal 3- a current source. as the capacitor voltage reaches full charge, it is discharged again and the counter is decremented by one count. these transitions occur at t3 through t9. at t9, the counter has been decremented to 0. the fault logic is then cleared, the outputs are enabled, and the converter attempts to restart with a full soft-start cycle. the converter comes into regulation at t10.
slus507d ? january 2002 ? revised november 2005 13 www.ti.com application information setting the current limit connecting a resistor from vdd to ilim sets the current limit. a 15- a current sink internal to the device causes a voltage drop at ilim that is equal to the overcurrent threshold voltage. ensure that (v dd ?0.8 v) v ilim v dd . the tolerance of the current sink is too loose to do an accurate current limit. the main purpose is for hard fault protection of the power switches. given the tolerance of the ilim sink current, and the r ds(on) range for a mosfet, it is generally possible to apply a load that thermally damages the converter. this device is intended for embedded converters where load characteristics are defined and can be controlled. soft-start and shutdown these two functions are common to the ss/sd pin. the voltage at this pin is the controlling voltage of the error amplifier during startup. this reduces the transient current required to charge the output capacitor at startup, and allows for a smooth startup with no overshoot of the output voltage if done properly. a shutdown feature can be implemented as shown in figure 5. c ss udg?01143 ss/sd 4 TPS40000 shutdown 3 a figure 5. shutdown implementation the device shuts down when the voltage at the ss/sd pin falls below 120 mv. because of this limitation, it is recommended that a mosfet be used as the controlling device, as in figure 5. an open-drain cmos logic output would work equally well. rectifier zero-current both the TPS40000 and tps40002 parts are source-only, thus preventing reverse current in the synchronous rectifier. synchronous rectification is terminated by sensing the voltage, sw with respect to ground, across the low-side mosfet. when sw node is greater than ?7 mv, rectification is terminated and stays off until the next pwm cycle. in order to filter out undesired noise on the sw node, the zero-current comparator is blanked for 75 ns from the time the rectifier is turned on. the tps40001 and tps40003 parts enable the zero-current comparator, (and therefore prevent reverse current), while soft-start is active. however, when the output reaches regulation; that is, at the end of the soft-start time, this comparator is disabled to allow the synchronous rectifier to sink current.
slus507d ? january 2002 ? revised november 2005 14 www.ti.com application information the following pages include design ideas for a few applications. for more ideas, detailed design information, and helpful hints, visit the TPS40000 resources at http://power.ti.com. fds6894a udg?02081 22 f 12.1 k ? 1 k ? 16.9 k ? 22 f 22 f 2.2 ? .0033 f 22 f 1 f 15 k ? 8.66 k ? 1 f 4.7 nf 68 pf 1 nf 5 8 7 10 9 1 2 3 ilim fb comp gnd hdrv sw vdd ldrv 4 ss/sd 6 boot tps40002/3/5 fds6894a 1.2 v 5 a 3.3 v pwp 470 pf 1.0 h 3.3 ? v out v dd figure 6. small-form factor converter for 3.3 v to 1.2 v at 5 a.
slus507d ? january 2002 ? revised november 2005 15 www.ti.com application information 5 8 7 10 9 1 2 3 ilim fb comp gnd hdrv sw vdd ldrv 4 c14 4.7 nf ss/sd 6 boot TPS40000/1/4 si4866dy 1.2 v 10 a 3.3 v si4866dy pwp + + udg?02082 1.5 h 392 ? 1200 pf 10 k ? 14 k 1.8 ? 1.8 ? 1 f 2.2 nf 6.19 k ? 1 f 22 f 330 f 22 f 330 f 82 pf 2.2 ? 10 nf 11 k ? 22 f 22 f 3.3 ? 22 f 22 f 22 f v dd v out figure 7. high-current converter for 3.3 v to 1.2 v at 10 a.
slus507d ? january 2002 ? revised november 2005 16 www.ti.com application information udg?02083 22 f 22 f 536 ? 6.19 k ? 2.2 ? 1000 pf 8.66 k ? 3.3 nf 1 f 22 f 1 f 1.8 ? 1500 pf 1.8 ? 5.62 k ? 15 k ? 100 pf 22 f 1.0 h l1 5 8 7 10 9 1 2 3 ilim fb comp gnd hdrv sw vdd ldrv 4 4.7 nf ss/sd 6 boot tps40002/3/5 fds6894a fds6894a 1.2 v 5 a 2.5 v bat54 pwp v out v dd 3.3 ? figure 8. ultra-low-input voltage converter for 2.5 v to 1.2 v at 5 a
slus507d ? january 2002 ? revised november 2005 17 www.ti.com application information udg?02084 24.9 k ? 820 pf 470 pf 22 f 330 f 330 f 2.2 nf 12.7 k ? 11 k ? 1.8 ? 1.8 ? 1 f 1 f 22 f 0.01 f 2.2 ? 470 f 1.27 k ? 9.76 k ? 1.0 h l2 5 8 7 10 9 1 2 3 ilim fb comp gnd hdrv sw vdd ldrv 4 4.7 nf ss/sd 6 boot TPS40000/1/4 q1 si4866dy vout 2.5 v 10 a vdd 3.3 v + q2 si4866dy pwp + + 22 f 22 f 22 f 3.3 ? figure 9. ultra-high-efficiency converter for 3.3 v to 2.5 v at 10 a
slus507d ? january 2002 ? revised november 2005 18 www.ti.com typical characteristics figure 10 v in ? input voltage ? v oscillator frequency percent change vs input voltage 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 1 2 3 4 5 6 ? f osc ? change in oscillator frequency ? % figure 11 temperature ? c ? f osc ? change in oscillator frequency ? % ?50 ?25 0 25 50 75 100 125 ?6 ?5 ?4 ?3 ?1 0 1 ?2 oscillator frequency percent change vs temperature figure 12 v in ? input voltage ? v v fb ? feedback voltage ? v feedback voltage vs input voltage 0.6990 0.6995 0.7000 0.7010 0.7005 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 figure 13 v fb ? feedback voltage ? v feedback voltage vs temperature temperature ? c 0.693 0.695 0.697 0.699 0.703 0.705 0.707 0.701 ?50 ?25 0 25 50 75 100 125
slus507d ? january 2002 ? revised november 2005 19 www.ti.com typical characteristics figure 14 v in ? input voltage ? v i limit ? sink current limit ? a current limit sink current vs input voltage 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 14.0 14.5 15.5 13.0 12.5 13.5 15.0 figure 15 current limit sink current vs temperature temperature ? c 14.0 14.5 15.0 15.5 16.0 ?50 ?25 0 25 50 75 100 125 i limit ? sink current limit ? a figure 16 t ? time ? 1 ms/div overcurrent ss/sd node (1 v/div) sw node (2 v/ div) figure 17 typical predictive delay switching ldrv (2 v/div) sw node (2 v/ div) t ? time ? 400 ns/div
package option addendum www.ti.com 10-aug-2016 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples TPS40000dgq active msop- powerpad dgq 10 80 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim -40 to 85 40000 TPS40000dgqg4 active msop- powerpad dgq 10 80 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim -40 to 85 40000 TPS40000dgqr active msop- powerpad dgq 10 2500 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim -40 to 85 40000 TPS40000dgqrg4 active msop- powerpad dgq 10 2500 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim -40 to 85 40000 tps40001dgq nrnd msop- powerpad dgq 10 80 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 40001 tps40001dgqr nrnd msop- powerpad dgq 10 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 40001 tps40001dgqrg4 nrnd msop- powerpad dgq 10 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 40001 tps40002dgq active msop- powerpad dgq 10 80 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 40002 tps40002dgqg4 active msop- powerpad dgq 10 80 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 40002 tps40002dgqr active msop- powerpad dgq 10 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 40002 tps40003dgq nrnd msop- powerpad dgq 10 80 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 40003 tps40003dgqg4 nrnd msop- powerpad dgq 10 80 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 40003 tps40003dgqr nrnd msop- powerpad dgq 10 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 40003 tps40003dgqrg4 nrnd msop- powerpad dgq 10 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 40003 tps40004dgq nrnd msop- powerpad dgq 10 tbd call ti call ti -40 to 85 40004 tps40004dgqr nrnd msop- powerpad dgq 10 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 40004 tps40005dgqr nrnd msop- powerpad dgq 10 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 40005
package option addendum www.ti.com 10-aug-2016 addendum-page 2 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TPS40000dgqr msop- power pad dgq 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 q1 tps40001dgqr msop- power pad dgq 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 q1 tps40002dgqr msop- power pad dgq 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 q1 tps40003dgqr msop- power pad dgq 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 q1 tps40004dgqr msop- power pad dgq 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 q1 tps40005dgqr msop- power pad dgq 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 q1 package materials information www.ti.com 24-feb-2016 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) TPS40000dgqr msop-powerpad dgq 10 2500 346.0 346.0 35.0 tps40001dgqr msop-powerpad dgq 10 2500 370.0 355.0 55.0 tps40002dgqr msop-powerpad dgq 10 2500 346.0 346.0 35.0 tps40003dgqr msop-powerpad dgq 10 2500 370.0 355.0 55.0 tps40004dgqr msop-powerpad dgq 10 2500 346.0 346.0 35.0 tps40005dgqr msop-powerpad dgq 10 2500 346.0 346.0 35.0 package materials information www.ti.com 24-feb-2016 pack materials-page 2
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